This invention relates to a method of manufacturing a bipolar semiconductor device for a high speed logic operating circuit or for an analog operating circuit in a high frequency range.
The performance of a bipolar transistor adapted for a high speed logic operation or an analog operation in a high frequency range has been improved by various means, such as forming a shallow junction in a vertical direction, separating elements by a buried oxide film or a trench structure to reduce a parasitic capacity between a substrate and a collector, and decreasing a parasitic capacity between a base and a collector and between the base and an emitter as well as a base resistance by fine lithographic technique and self-alignment technique.
More particularly, a transistor used before employing the above-mentioned means is constructed as shown in a sectional view of FIG. 1. This transistor is of npn type. P type base diffusion region 1 is formed in an n type substrate or n type epitaxial layer N type emitter diffusion region 2 is further formed in base diffusion region 1. Base electrode 3 and emitter electrode 4 made of metal are formed to contact with base diffusion region 1 and emitter diffusion region 2, respectively.
In order to improve the high frequency characteristic of a bipolar transistor, it is necessary to reduce a parasitic resistance and a parasitic capacitance and, particularly to, reduce base resistance rbb' and collector-base junction capacity Cjc. In a transistor of conventional structure shown in FIG. 1, rbb' is determined according to distance L1 from the contacting position of base electrode 3 to emitter diffusion region 2, and can be reduced when distance L1 is decreased. However, the limit of reduction in distance L1 is determined according to the margin in alignment of electrodes 3 and 4 with contact holes and to distance L2 determined by the design rule in photolithographic step for the electrode metal. Junction capacity Cjc decreases when width L3 of base diffusion region 2 is reduced, however this limit is determined according to the design rule in lithographic step for the electrode metal. Thus, the conventional structure shown in FIG. 1 cannot effectively reduce base resistance rbb' and collector-base junction capacity Cjc.
Japanese Patent Publication No. 41826/1982 official gazette discloses an invention to eliminate the abovedescribed drawback. A transistor of the invention disclosed in the official gazette employs a base leading electrode structure with a polycrystalline silicon layer, and shown in sectional view in FIG. 2. The transistor is of npn type. P type base diffusion region 1 is formed in an n type substrate or an n type epitaxial layer. N type emitter diffusion region 2 is formed in base diffusion region 1. Emitter electrode 3 made of metal is formed to contact directly emitter diffusion region 2, and base diffusion region 1 is connected via p.sup.+ type polycrystalline silicon film 5 to base electrode 4. With such a structure, it is not necessary to extend base diffusion region 1 to the lower portion of base electrode 4, thereby reducing width L4 of base d1ffueion region 1. Thus, collector-base junction capacity Cjc can be reduced to a certain degree. In this structure, base resistance rbb' is determined according to distance L5 from the contact of polycrystalline silicon film 5 with base diffusion region 1 to emitter diffusion region 2, and rbb' can be reduced to a certain degree.
However, contact position of polycrystalline silicon film 5 with base diffusion region 1 and distance L5 from the contact position to a opening for used in diffusing an impurity to emitter diffusion region 2 are not determined in self-alignment manner, and collector-base junction capacity Cjc and base resistance rbb' cannot be sufficiently reduced.
U.S. Pat. No. 4,284,362 is heretofore known as an example of reducing base resistance rbb' by forming a base electrode leading polycrystalline silicon layer and a window for used in diffusing an impurity in an emitter diffusion region in a self-alignment manner. In a method for manufacturing a transistor according to this patented invention, as shown in sectional view in FIG. 3, base leading electrode forming polycrystalline silicon layer 6 and first insulating film 7 are sequentially formed on a single crystal silicon substrate made of P.sup.- type layer, N.sup.+ type layer, N type layer and P type layer. Opening 8 is formed on emitter and base active regions, second insulating film 9 is grown on the structure. Second insulating film 9 is selectively removed by anisotropically dry etching to allow second insulating film 9 to remain only on the side walls of first insulating film 7 and base leading electrode polycrystalline silicon layer 6. The position of the emitter diffusion region and the position of base leading electrode forming polycrystalline silicon layer 6 are determined in a self-alignment manner by means of second insulating film 9 remaining on the side walls. Thus, the emitter diffusion region and the polycrystalline silicon layer 6 are positioned in the minimum distance therebetween, thereby reducing the base resistance.
However, when removing second insulating film 9 by anisotropically dry etching, the surface of primary single crystal silicon substrate is exposed with plasma atmosphere of chlorine gas used, thereby causing the emitter diffusion region formed in the later step to be damaged. Moreover, a difficulty arises in providing selectivity under anisotropically dry etching between the polycrystalline silicon layer and the emitter diffusion region made of single crystal silicon. Another difficulty arises in detection of the completion of the etching, and it lacks mass productivity.
The anisotropically dry etching technique is advantageous in that it provides semiconductor devices with a high working accuracy. Thus, the dry etching technique is necessarily indispensable in the method of this type.
As described above, the conventional technique has various drawbacks, such as damages to the active region done by anisotropically dry etching, reduction of the production yield, low mass-productivity, and insufficient the base resistance.